Integrated circuit (IC) design generally involves rendering a particular IC layout as a series of polygons outlining various IC features and interconnections. Various IC design tools are available to assist in defining these features and functions and storing them in a standardized format such as in a GDSII database file format, which consists of a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The structured and 3D layered layout can then be used to map out and manufacture the IC.
To reverse engineer a particular IC layout, sequential images of the IC are taken and mosaicked, layer-by-layer, and processed to digitally reconstruct the IC layout. Automated IC feature extraction tools have been developed to automatically identify IC features and connections from these images and progressively reconstruct IC layout polygons, which may again be represented and stored in a standardized format such as in a GDSII database file format. However, as source IC imaging, mosaicking, and layering generally yields certain inaccuracies and imprecisions when automatically processed for feature extraction, manual and/or semi-automated post-processing is generally required to address misalignments, missed connections, artefacts and errors, for example, which may be expected when working from source images rather than a known layout design.
In current implementations, such manual or semi-automated processes can be executed by a team working in parallel on different regions of interest, whereby corrected polygons in any given region may predictably impact identified polygons in other related regions and/or layers such that polygon corrections are generally propagated on-the-fly throughout the layout by reprocessing the entire layout polygon data. For increasingly large and complex polygon data structures representative of increasingly complex and dense IC designs, the on-the-fly propagation of polygon corrections/adjustments, particularly across a team working in parallel on a same reverse engineered design layout, can draw significant processing resources and lead to significant if not prohibitive lag time between iterations.
This background information is provided to reveal information believed by the applicant to be of possible relevance. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art or forms part of the general common knowledge in the relevant art.